Robotics

Real time, Low Power Sense and Control

Robotics enable improved quality, increased productivity and efficiency in traditional manufacturing, and are rapidly expanding into Warehouse and Supply Automation, Mining, Farming, and Smart City applications. Lattice FPGAs are optimized for the unique requirements that Robotics applications demand:

  • Low power, deterministic sense and control
  • Real time Industrial Networking
  • Machine vision, depth sensing
  • Ssensor fusion
  • Motor & Motion Control
  • Artificial Intelligence
  • HW-based Secure Root of Trust

Lattice FPGAs are optimized for Robotics, offering the following benefits:

  • Up to 75% lower power than similar FPGAs
  • Small form factors – from 4mm x 4mm
  • 100x better SER vs other SRAM based FPGAs
  • Optimized Sensor Interfacing
  • Scalable Performance
  • Lattice Stacks: mVision, sensAI, and Sentry

Lattice solutions stacks provide ready-to-go flexible IP building blocks, reference designs and platforms to further speed development of products.

Robotics

Jump to

Block Diagram

Robotics Block Diagram

Example Use Cases

Machine Vision Camera Processing

  • Sensor Interface, Hardened MIPI, SLVS EC, LVDS
  • Customizable ISP for image processing
  • sensAI Artificial Intelligence for object/defect detection
  • Interface - GigE Vision, USB3 Vision, CoaxPress

Edge AI Processing

  • Bridge one or multiple CSI-2 image sensors to processor interface
  • Up to 3 Mb of internal RAM for processing
  • Offloads inferencing from CPU for object detection / counting
  • Combine video bridging and edge AI into a single device

Depth Sensing

  • Stereo Vision Reference Design
  • Depth Sensing
  • Collision Avoidance

Multi Axis Motor Control

  • High Performance
  • Multi-Axis
  • Real time sense & control
  • Internal Soft CPU or External CPU

Reference Designs

Key Phrase Detection

Reference Design

Key Phrase Detection

Continuous searches for a key phrase utterance via a digital MEMS microphone. Can be re-configured to work with any trained word or phrase.
Key Phrase Detection
Human Face Identification

Reference Design

Human Face Identification

Uses a Convolutional Neural Network in the ECP5 FPGA to detect a human face, and match to known registered faces. Can be adapted to work with any other object.
Human Face Identification
Human Presence Detection

Reference Design

Human Presence Detection

Uses Lattice sensAI IP to continuously search for the presence of a human and reports results. Can be adapted to detect any other object.
Human Presence Detection
Object Counting

Reference Design

Object Counting

An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
Object Counting

Demos

Key Phrase Detection

Demo

Key Phrase Detection

Uses artificial intelligence (AI) to detect a specific key-phrase using a tiny, low-power iCE40 UltraPlus FPGA
Key Phrase Detection
4 Input to 1 Output MIPI CSI-2 Image Aggregation Demo

Demo

Hand Gesture Detection

Demo

Hand Gesture Detection

Uses artificial intelligence (AI) to implement hand gesture detection algorithm using a tiny, low-power iCE40 UltraPlus FPGA
Hand Gesture Detection
Human Counting

Demo

Human Counting

Human upper-body detection and counting demonstration utilizes Lattice’s ECP5 FPGA and a Convolutional Neural Network (CNN) acceleration engine
Human Counting
Human Face Detection

Demo

Human Face Detection

Uses Lattice sensAI IP to detect human faces on a tiny, low-power iCE40 UltraPlus FPGA implementing AI at the edge. Adaptable to detect other objects.
Human Face Detection

IP Cores

CNN Accelerator IP

IP Core

CNN Accelerator IP

Implement AI solutions with CNNs from common or custom networks. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
CNN Accelerator IP
CNN Compact Accelerator IP

IP Core

CNN Compact Accelerator IP

Implement AI solutions with CNNs or BNNs that have power consumption in the mW range. Works with Lattice Neural Network Compiler software tool.
CNN Compact Accelerator IP
CNN Plus Accelerator IP

IP Core

CNN Plus Accelerator IP

Implement Ultra-Low Power AI solutions with CNNs. Configure up to 16-bit widths. Works with Lattice Neural Network Compiler software tool.
CNN Plus Accelerator IP
CSI-2/DSI D-PHY Receiver

IP Core

CSI-2/DSI D-PHY Receiver

Modular MIPI/D-PHY IP - PHY for receiving MIPI CSI-2/DSI Data for further processing. Supports up to 4 MIPI lanes to 10Gb/s
CSI-2/DSI D-PHY Receiver

Development Kits & Boards

Embedded Vision Development Kit

Board

Embedded Vision Development Kit

Three-board Video Interface Platform (VIP) modular kit. Includes 2 MIPI/D-PHY camera input, FPGA processing, HDMI output. More Input/Output boards available.
Embedded Vision Development Kit
USB3-GbE VIP IO Board

Board

USB3-GbE VIP IO Board

Output board for Video Interface Platform (VIP) and Embedded Vision Development Kit - adds video over USB 3.0 and Gigabit Ethernet.
USB3-GbE VIP IO Board
HM01B0 UPduino Shield

Board

HM01B0 UPduino Shield

A complete development kit for implementing Artificial Intelligence (AI) using vision and sound as sensory inputs to a low-cost, low-power iCE40 UltraPlus FPGA.
HM01B0 UPduino Shield
DisplayPort VIP Input Board

Board

DisplayPort VIP Input Board

Expands the Lattice VIP board ecosystem to support DisplayPort 1.4a (DP) video input - up to 4 lanes at 1.62 or 2.7 Gbps.
DisplayPort VIP Input Board

Support

Quality & Reliability

Reference Material to Help Answer Your Questions

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