In-Vehicle Infotainment

Reliable, Secure, Low Power FPGA for IVI Applications

With increasing adoption of mobile-influenced technologies in the modern cars, consumers are expecting smart phone features and functionalities in their car infotainment systems. Lattice’s auto grade FPGAs provide flexible, reliable, safe, and secure integration for In-Vehicle Infotainment (IVI) at lowest power.

  • Enabling low latency multi-sensor interfaces with image processing for realtime information for around vehicle driver awareness
  • Enabling multitude of sensor and display interfaces with smart Human Machine Interface (HMI) using Lattice’s sensAI for In-Vehicle Infotainment systems
  • Enabling reliable, safe, and secure hardware authentication to protect against cyber-attacks while ensuring safety using Lattice FPGA’s hardware-based security and Functional Safety (FuSa)
IVI

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Block Diagram

Infotainment Systems Overview

Example Use Cases

360° Surround View using CrossLink-NX or ECP5 FPGA

  • 360° Surround-view monitoring system
  • Single-chip 4 camera aggregation & ISP solution
  • Interface to different camera sensors and display devices
  • Low latency and future proof

E-Mirror Application using CrossLink-NX, ECP5, or LatticeXP2 FPGA

  • The camera sensor and Display interface support
  • Low power consumption for better thermals
  • Single-chip sensor aggregation and ISP solution
  • Promotes driver safety with better blind spot detection and night vision

Sensor Fusion & Aggregation over MIPI SERDES using CrossLink-NX

  • Up to 14 sensor aggregation with virtual channel support
  • Large on-chip memory for the faster frame and edge processing
  • Up to 10Gbps MIPI CSI-2 support for interface with MIPI SERDES technologies
  • Low power device with smaller footprint and security

Full-Featured ISP Pipeline for CrossLink-NX and ECP5

  • Full functional universal Image Signal Processing pipeline
  • User-configurable parametrizable IP
  • An image sensor interface independent with support for High Dynamic Range (HDR)
  • Optimized Lattice FPGA architecture

Sensor aggregation with transmission up to 10m

  • Real-time image and data transfer using Auto SERDES chipsets
  • Sensor aggregation and fast data transfer without skew
  • Longer and cheaper wiring with low EMI
  • Heterogeneous sensor interfaces with FPGAs

Driver Display overlay using CrossLink-NX and ECP5

  • Flexibility to support multiple display interfaces, like DSI, eDP
  • Display processor functionality that is configurable
  • Overlay capability of driver notifications at low power solution for better thermals

Hardware-based SecureBoot and Supply Chain Security

  • NIST compliant Platform Firmware Resiliency (PFR) for ADAS/ DA Domain Controllers
  • Real-time Protect, Detect and Recover for non-bypassable security to cover vulnerable attack points
  • Scalable solution with nanosecond level response for all firmware on the board

Reference Designs

MIPI CSI-2 Virtual Channel Aggregation

Reference Design

MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

Reference Design

MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge

Modular MIPI/D-PHY Reference Design - Complete solution integrates the Byte to Pixel Converter, CSI-2/DSI D-PHY Receiver and FPD-LINK (OpenLDI) Transmitter
MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge
N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

Reference Design

Demos

4 Input to 1 Output MIPI CSI-2 Image Aggregation Demo

Demo

DisplayPort Receive Demo

Demo

DisplayPort Receive Demo

Uses Bitec's DisplayPort IP core on the ECP5 FPGA in Lattice's Embedded Vision Development Kit. Compliant with DisplayPort 1.4a (including eDP 1.4 support).
DisplayPort Receive Demo
DisplayPort Transmit Demo

Demo

DisplayPort Transmit Demo

Uses Bitec's DisplayPort IP core on the ECP5 FPGA in Lattice's Embedded Vision Development Kit. Compliant with DisplayPort 1.4a (including eDP 1.4 support).
DisplayPort Transmit Demo
3D Depth Mapping

Demo

3D Depth Mapping

Determines the distance between an embedded device and an object using a Semi-Global Block Matching (SGBM) algorithm to determine 64 different disparity levels
3D Depth Mapping

IP Cores

CSI-2/DSI D-PHY Receiver

IP Core

CSI-2/DSI D-PHY Receiver

Modular MIPI/D-PHY IP - PHY for receiving MIPI CSI-2/DSI Data for further processing. Supports up to 4 MIPI lanes to 10Gb/s
CSI-2/DSI D-PHY Receiver
FPD-LINK Receiver

IP Core

FPD-LINK Receiver

Modular MIPI/D-PHY IP - Converts FPD-LINK Video Streams to Pixel Clock Domain
FPD-LINK Receiver
FPD-LINK Transmitter

IP Core

FPD-LINK Transmitter

Modular MIPI/D-PHY IP - Convert Pixel Data Streams to an FPD-LINK Video Stream
FPD-LINK Transmitter

Automotive Quality & Safety Standard

Support

Quality & Reliability

Reference Material to Help Answer Your Questions

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