Lattice Propel Design Environment

Build FPGA-based Processor Systems in Minutes

Related Products

Design Environment for Lattice FPGA - based Processor System Design - Lattice Propel is a complete set of graphical and command-line tools to create, analyze, compile, and debug both the hardware design of an FPGA-based processor system, and the software design for that processor system.

Lattice Propel Builder - An easy to use system IP integration environment, Propel Builder provides tools to integrate processors and peripheral IP. The graphical integration environment features an easy to use drag and drop correct by construction methodology. All commands are Tcl scriptable.

Lattice Propel SDK - A seamless software development environment, Propel SDK is a software development kit (SDK) with an integrated industry standard IDE and toolchain. The SDK features SW/HW debugging capabilities along with software libraries and board support packages (BSP) for Propel Builder defined systems.

Features

  • Drag and drop IP instantiation
  • Correct by construction design methodology
  • High productivity HW/SW debugging
  • Software libraries and BSP support
  • Tcl scripting commands

Getting Started

  1. Download: choose and download foftware from the Software Downloads & Documentation table below
  2. Install: follow the installation guide, found in Software Downloads & Documentation section below.
  3. License: You will need a Lattice Propel license, Click the button below to request a license.

Jump to

Block Diagrams

Lattice Propel Design Environment

Lattice Propel Builder Design Flow

Lattice Propel Solutions

RISC-V MC CPU IP Core

IP Core

RISC-V MC CPU IP Core

Propel IP Module: 32-bit RISC-V processor core with optional Timer and PIC sub-modules, connects via AHB-Lite bus to other Propel IP modules and more.
RISC-V MC CPU IP Core
AHB-Lite Interconnect Module

IP Core

AHB-Lite Interconnect Module

Propel IP Module: Fully parameterized interconnect for AHB-Lite systems - bus widths of 8 to 1024 bits, address widths up to 32 bits, 32 masters and 32 slaves.
AHB-Lite Interconnect Module
AHB-Lite to APB Bridge Module

IP Core

AHB-Lite to APB Bridge Module

Propel IP Module: Bridges high-speed AHB-lite to low-power APB. Data bus widths up to 32 bits. Address width up to 32 bits.
AHB-Lite to APB Bridge Module
APB Interconnect Module

IP Core

APB Interconnect Module

Propel IP Module: Fully parameterized to connect up to 32 APB bus masters and 32 slaves. Data bus width up to 32 bits. Address width up to 32 bits.
APB Interconnect Module
EFB Module

IP Core

EFB Module

Propel IP Module: Implements the Embedded Function Block (EFB) in MachXO3D, including I2C, Configuration Blocks and User Flash Memory with an APB Interface.
EFB Module

Software Downloads & Documentation

Quick Reference
Information Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Propel 1.0 API Reference
FPGA-AN-02027 1.0 6/3/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Propel 1.0 Installation Guide
FPGA-AN-02026 1.0 6/3/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Propel Builder 1.0 User Guide
1.0 6/3/2020
Lattice Propel 1.0 User Guide
FPGA-UG-02110 1.0 6/3/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Propel Product Brochure
IO272 1.0 6/3/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Propel 1.0 Release Notes
FPGA-AN-02025 1.0 6/3/2020
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Propel 1.0
1.0 6/2/2020 EXE 470.2 MB
NGO Encryption Pack
1.0 7/3/2020


Licensing

Currently, Lattice Propel Design Environment only requires a Free License.

Device Support

Device Support by License
Product Subscription License Free License
MachXO3D
Check Mark
 
Request License

Propel Feature List

  • Propel Builder – Graphical driven IP integration and system building tool drag and drop instantiation and wizard guided configuration and parameterization.
  • Propel SDK – Software development kit with Industry-standard IDE and toolchain with integrated Gnu Debugging (GDB).
  • Templates for Hello World project
  • System-level functional verification environment for templates
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